The present invention relates, in general, to the field of integrated circuit (IC) devices. More particularly, the present invention relates to a low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM.
DRAM memory devices incorporate one or more arrays of memory cells, each generally consisting of a single transistor and associated capacitor. The transistor has one terminal coupled to an associated bit line and its gate coupled to a word line. Another terminal is generally coupled to circuit ground through the capacitor and by enabling the transistor via the word line, the charge on the capacitor may be placed on the associated bit line. Due to the dynamic nature of the charge stored in the capacitor, it must be periodically refreshed to replenish the leaked charge.
A “refresh” or “active” command can occur on any clock cycle in an integrated circuit memory, requiring internal (on-chip) detection of the cycle type being executed. This detection process slows down the row address path within the device. On-chip refresh circuitry has been incorporated in DRAM designs for several decades. When first introduced, a separate refresh pin was used to inform the DRAM to execute a refresh operation using internally generated addresses instead of a normal, externally supplied row address. Later, /CAS-before-/RAS (CAS=column address strobe, and RAS=row address strobe) commands were used to enable on-chip refresh cycles. When /CAS was “high” and /RAS went “low”, a normal row selection was done using the external address supplied to the time when /RAS went “low”. However, if /CAS was “low” when /RAS went “low”, then a refresh operation was executed using an internally generated refresh address.
Conventional DRAMs currently support two different types of refresh operations: auto-refresh and self-refresh. Auto-refresh uses a specific command instruction: /CS (chip select), /RAS, and /CAS “low” with /WE (write enable) “high” that is sampled at the rising edge of the DRAM's input clock signal. The self-refresh command is similar to auto-refresh, but occurs concurrently with entering power-down mode. In self-refresh operation, the device periodically executes refresh cycles (which are self-timed) to maintain stored data integrity during power-down mode.
In the past, incorporating on-chip refresh techniques using the methods described above had little impact on device performance. However, as the operating frequency of DRAMs and SDRAMs has increased, the inclusion of on-chip refresh using conventional methods has had an impact on row access performance. With present methods, during any cycle that an active command can be executed, a refresh command could have been executed instead, provided the device had been previously idle (in precharge state.) For this reason, the on-chip circuitry must hold-off row selection while the appropriate address is selected, depending on whether the present instruction is an “active” or a “refresh” command. This process is complicated in most instances and a command address latch is used to hold either the externally supplied row address or the internally generated address from the refresh address counter depending on the command. As clock rate increases, the operational time penalty due to selecting which address to use before row selection can be enabled will become a larger percentage of the row select time.
Further, with conventional DRAM-based memory technology, open memory banks must be closed prior to the issuance of a “refresh” command. These banks are required to be closed by issuing individual “precharge” commands to open banks using a “precharge all” to close open banks or “auto-precharge” commands for “read” or “write” cycles to ensure that an opened bank has been closed (or precharged) prior to issuing a refresh command.
Despite these technological advances, conventional memory devices, and those incorporating embedded memory, do not accurately time when a refresh operation is required over all possible process corners, voltages and temperatures (PVT) and do not sufficiently lower transistor leakage power in all circuit blocks accordingly. Further, conventional techniques do not employ “active” power-gating techniques wherein various circuit blocks can be powered-up or powered-down as required during a refresh operation.